This invention relates to a semiconductor memory device with a circuit which is supplied with, in particular, a low power voltage from the outside and generates a high negative or positive voltage.
FIG. 1 is a view, showing a general flash memory cell. The flash memory uses, as a memory cell, a stacked-gate transistor which has a floating gate FG and a control CG.
This memory cell performs data programming and erasing when electrons are injected into the floating gate FG and discharged therefrom to vary the threshold voltage of the memory cell. Therefore, it is necessary to set various potential relationships between the voltage Vg of the gate (control gate CG) of the memory cell, the voltage Vd of the drain (D) thereof, and the voltage Vs of the source (S) thereof. FIG. 2 shows examples of voltages applied to each element of the memory cell at the time of data reading, programming and erasing.
The external power of a flash memory which performs hot electron writing is provided in the form of a combination of two powers of VCC=5 V and VPP=12 V, a single power of VCC=5 V, or a single power of VCC=3 V. The external power is converted, before being to the memory cell, to a voltage suitable for the cell by a boosting circuit and a negative voltage generating circuit incorporated in the memory device.
For example, in the case of the single power of VCC=5 V, a gate voltage Vg of 10 V or more is generated by the boosting circuit at the time of programming, while a gate voltage Vg of -10 V is generated by the negative voltage generating circuit at the time of erasing, as is shown in FIG. 2. In the case of the single power of VCC=3 V, it is necessary to generate, using the booster circuit, a gate voltage Vg of 10 V or more and a drain voltage of Vd of 5 V at the time of programming and a source voltage Vs of 5 V at the time of erasing. On the other hand, it is necessary to generate a gate voltage Vg of -10 V at the time of erasing, using the negative voltage generating circuit.
FIG. 3 is a circuit diagram, showing the structure of the negative voltage generating circuit. This structure is applied to a flash memory with the single power of VCC=5 V. As is shown in FIG. 3, the current paths of P-channel MOS transistors T1, T2 and T3 for signal transfer are connected in series between the ground terminal and an output terminal VOUT. Capacitors C1 and C2 are connected to nodes N1 and N2 between the transistors T1 and T2, and T2 and--T3, respectively. The other electrodes of the capacitors C1 and C2 are disposed to receive pulse signals OSC1 and OSC2, respectively. The gates of the transistors T1-T3 are connected to capacitors C3-C5, respectively. The other electrodes of the capacitors C3-C5 are disposed to receive pulse signals OSC3, OSC4 and OSC3, respectively.
Each of P-channel MOS transistors T10, T20 and T30 has its current path connected between the gate and drain of a corresponding one of the transistors T1, T2 and T3. The gates of the transistors T10, T20 and T30 are connected to the sources (nodes N1-N3) of the transistors T1-T3, respectively. In other words, the transistors T10, T20 and T30 are provided for compensating for the threshold voltages of the transistors T1-T3 which serve as diodes. The gates of the transistors T1-T3 are connected to nodes N10, N20 and N30, respectively.
The FIG. 3 circuit generates a negative voltage at the terminal VOUT when the pulse signals OSC1, OSC2, OSC3, OSC4 and OSC3 are input to the capacitors C1-C5, respectively. The pulse signals OSC1, OSC2, OSC3, OSC4 and OSC3 have waveforms as shown in FIG. 4 and are output from a pulse generating circuit which will be described below.
FIG. 5 is a circuit diagram, showing an example of a pulse generating circuit for generating the pulse signals shown in FIG. 4. This pulse generating circuit comprises a ring oscillator (A) for generating a signal of a voluntary cycle, and a pulse forming circuit (B) for converting the output of the oscillator to a voluntary waveform.
The ring oscillator (A) is constituted by a number (2 n+1) of inverters arranged in series (the FIG. 5 case includes a NAND gate 11 and inverters 12-19, i.e. nine inverters). Signals RO1, RO2, RO3 and RO4 are output from the junctions between the inverters 12 and 13, between the inverters 14 and 15, between the inverters 16 and 17 and between the inverters 18 and 19, respectively.
One input OSCE of the NAND gate 11 is set at "H" (high level) to operate the ring oscillator (A), and at "L" (low level) to stop it. Each of the outputs RO1-RO4 is supplied to a corresponding one of the input terminals of the pulse forming circuit (B).
The pulse forming circuit (B) includes a series circuit of a NOR gate 211 and inverters 221 and 231, a series circuit of a NOR gate 212 and inverters 222 and 232, a series circuit of a NAND gate 213 and inverters 223 and 233, and a series circuit of a NAND gate 214 and inverters 224 and 234. The NOR gate 211 receives the outputs RO2 and RO3 of the ring oscillator (A), and the inverter 231 outputs the pulse signal OSC1. The NOR gate 212 receives the inverted signal of the output RO2 (a signal via the inverter 241) of the ring oscillator (A) and the inverted signal of the output RO3 (a signal via the inverter 242) of the same, and the inverter 232 outputs the pulse signal OSC2. The NAND gate 213 receives the inverted signal of the output RO1 (a signal via the inverter 243) and the inverted signal of the output RO4 (a signal via the inverter 244), and the inverter 233 outputs the pulse signal OSC3. The NAND gate 214 receives the outputs RO1 and RO4 of the ring oscillator (A), and the inverter 234 outputs the pulse signal OSC4.
The output pulse signals OSC1-OSC4 of the pulse generating circuit of FIG. 5 have waveforms as shown in FIG. 4. P-channel MOS transistors and N-channel MOS transistors incorporated in CMOS inverters which constitute the last-stage inverters 231-234 in the pulse forming circuit (B) are connected to a power voltage terminal VCC and a ground terminal GND, respectively. Accordingly, the pulse amplitude (Vosc) of the pulse signals OSC1-OSC4 is VCC.
Referring to FIG. 4, the operation of the negative voltage generating circuit with the circuit structure shown in FIG. 3 will be described. Specifically, how the level of the node N2 decreases will be explained with reference to t1-t4 modes in FIG. 4.
t1: The level of the pulse signal OSC1 falls. Accordingly, the level of the node N1 falls as a result of coupling with the capacitor C1. Further, the transistor T20 is turned on, thereby setting the nodes N1 and N20 at the same level.
t2: The level of the pulse signal OSC2 rises. Accordingly, the level of the node N2 rises as a result of coupling with the capacitor C2 (N1&lt;N2). Further, the transistor T20 is turned off, thereby shifting the node N20 into a floating state.
t3: The level of the pulse signal OSC4 falls. Accordingly, the level of the node N20 falls as a result of coupling with the capacitor C4. Further, the transistor T2 is turned on. In addition, since N1&lt;N2 at t2, a current flows from the node N2 to the node N1, thereby the level of the node N2 falls.
t4: The level of the pulse signal OSC4 rises.
Accordingly, the level of the node N20 rises as a result of coupling with the capacitor C4. Further, the transistor T2 is turned off, thereby shifting the node N2 into a floating state.
As described above, the level of the node N2 falls since a current flows to the node N1 via the transfer transistor T2. At this time, the greater the current, the greater the level drop of the node N2.
This means that the greater the gate voltage of the transistor T2, the greater the convenience, when the transistor T2 is turned on. In the conventional case, the amplitude Vosc of the pulse signal OSC4 is identical to VCC as described above. Specifically, the pulse generating circuit shown in FIG. 3 is operated by a power voltage of 5 V and generates a pulse signal with an amplitude Vosc of 5 V.
To obtain a VOUT voltage of -10 V in the negative voltage generating circuit of FIG. 3, a bias of -10 V is locally applied to the substrate. For example, as is shown in FIG. 6, the P-channel MOS transistor T3 for signal transfer is formed in an N-well in a P-type substrate, and provides an output VOUT from its source. Accordingly, when the VOUT voltage is -10 V, the potential of the N-well cannot be set at less than GND to avoid a P-N forward voltage, since the substrate potential is GND. If the N-well potential is set at GND, a back gate bias of -10 V is applied to the transistor T3.
As a result, as shown in FIG. 7, the threshold voltage (Vth) of the transfer transistor T3 is Vthp, which is higher than 3 V, due to the back gate bias effect. To turn on the transistor T3, its gate/source voltage Vgs needs to be higher than Vthp. Since at this time, the pulse signal OSC3 is applied to the capacitor C5 in FIG. 3, .vertline.Vgs.vertline..ltoreq.Vosc is established. In the conventional case where Vsoc=VCC, the threshold voltage of the transfer transistor increases to a value higher than the power voltage VCC because of the substrate bias effect, if the power voltage is more and more reduced. As a result, it is possible that a negative voltage may not be transferred.
As described above, in the negative voltage generating circuit incorporated in the conventional semiconductor memory device, the lower the negative voltage to be obtained, the greater the back gate bias voltage and the greater the threshold voltage of the transfer transistor. Accordingly, the lower the operation power voltage VCC, the lower the gate/source voltage Vgs of the transfer transistor. In other words, the lower the VCC, the lower the absolute value of the negative voltage to be obtained, and the higher the lower limit of the negative voltage. This can be also said of a positive voltage generating circuit. In this case, it is possible that the upper limit of a positive voltage to be obtained from the circuit may be lowered.